A flexible multi-channel high-resolution Time-to-Digital Converter ASIC

A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution (~25ps – 800ps binning) and a dynamic range of 102.4μs has been implemented in a 0.25μm CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 97.5ps. Finally, finer time interpolation is obtained using four samples of the DLL separated by 24.5ps generated by an adjustable on-chip RC delay line. In the lower resolution modes of operation, 32 TDC channels are available. In the highest resolution mode eight channels are available, since four low-resolution channels are used to perform a single fine time interpolation. The TDC is capable of measuring both leading and trailing edges of the input signal. Measurements are initially stored as time stamps in individual four-location deep asynchronous channel buffers. After proper encoding, measurements are written into four 256-deep derandomizing FIFO’s shared between all channels. This TDC may be operated in a triggered or non-triggered mode. Finally, data is written into a common 256-deep readout FIFO.